| ⊦ labs(gs, ls, pc, ags, als, apc) ↔ ls.t = als.t ∧ (pc = idle → apc = idle) ∧ (pc = ready → apc = ready) ∧ (pc = crashed → apc = crashed) ∧ (pc = R1 → apc = invRead) ∧ (pc = R2 ∨ pc = R3 ∨ pc = R4 → apc = resRead) ∧ (pc = W1 ∨ pc = W2 ∨ pc = W3 → apc = invWrite) ∧ (pc = W4 ∨ pc = W5 ∨ pc = W6 ∨ pc = W7 → apc = resWrite) ∧ (pc = R1 → ls.l = als.il) ∧ (pc = R2 ∨ pc = R3 ∨ pc = R4 → ls.v = als.ov) ∧ (pc = W1 ∨ pc = W2 ∨ pc = W3 ∨ pc = W4 ∨ pc = W5 ∨ pc = W6 ∨ pc = W7 → ls.l = als.il ∧ ls.v = als.iv) ∧ (pc = idle ∨ pc = ready ∨ pc = R1 ∨ pc = R4 ∨ pc = W1 ∨ pc = W5 → (∀ l. ¬ FO(ls.t) ∈ gs.p(l) → ((ags.h | l) | ls.t) | false = [])) ∧ (pc = W2 ∨ pc = W3 ∨ pc = W6 ∨ pc = W7 → (∀ l. ((ags.h | l) | ls.t) | false = [])) ∧ (pc = R2 ∨ pc = R3 → (∀ l0. l0 ≠ ls.l ∧ ¬ FO(ls.t) ∈ gs.p(l0) → ((ags.h | l0) | ls.t) | false = [])) ∧ (pc = R2 → gs.ctr(ls.l) = 0 → ((ags.h | ls.l) | ls.t) | false = []) ∧ (pc = W4 → ((ags.h | ls.l) | ls.t) | false = (W(ls.t, ls.l, ls.v), false) ' ∨ ((ags.h | ls.l) | ls.t) | false = []) |